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M28C16A M28C17A
16 Kbit (2Kb x8) Parallel EEPROM
FAST ACCESS TIME: - 150ns at 5V - 250ns at 3V SINGLE SUPPLY VOLTAGE: - 5V 10% for M28C16A and M28C17A - 2.7V to 3.6V for M28C16-xxW LOW POWER CONSUMPTION FAST WRITE CYCLE - 32 Bytes Page Write Operation - Byte or Page Write Cycle: 5ms ENHANCED END OF WRITE DETECTION - Ready/Busy Open Drain Output - Data Polling - Toggle Bit PAGE LOAD TIMER STATUS BIT HIGH RELIABILITY SINGLE POLYSILICON, CMOS TECHNOLOGY - Endurance >100,000 Erase/Write Cycles - Data Retention >40 Years JEDEC APPROVED BYTEWIDE PIN OUT DESCRIPTION The M28C16A and M28C17Aare 2K x8 low power Parallel EEPROM fabricatedwith STMicroelectronics proprietarysingle polysilicon CMOS technology. The device offers fast access time with low power dissipation and requires a 5V or 3V power supply. Table 1. Signal Names
A0-A10 DQ0-DQ7 W E G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage Ground
28
1
PDIP28 (BS)
PLCC32 (KA)
28
1
SO28 (MS) 300 mils
TSOP28 (NS) 8 x13.4mm
Figure 1. Logic Diagram
VCC
11 A0-A10
8 DQ0-DQ7
W E
M28C16A M28C17A RB
G
VSS
AI02109
August 1998
1/19
M28C16A, M28C17A
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
RB NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 28 2 27 3 26 4 25 5 24 6 23 7 22 M28C17A 8 21 9 20 10 19 11 18 12 17 13 16 14 15
AI02110
VCC W DU A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A6 A5 A4 A3 A2 A1 A0 NC DQ0
RB or NC (1) DU VCC W DU 1 32 A8 A9 NC NC G A10 E DQ7 DQ6 M28C16A M28C17A 25 17
AI02111
9
Warning: NC = Not Connected, DU = Don't Use.
Warning: NC = Not Connected, DU = Don't Use. Note: 1. Pin 2 is either RB for M28C17A or NC for M28C16A.
Figure 2C. SO Pin Connections
Figure 2D. TSOP Pin Connections
RB NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 M28C17A 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W DU A8 A9 NC G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
G NC A9 A8 DU W VCC RB NC A7 A6 A5 A4 A3
22
DQ1 DQ2 VSS NC DQ3 DQ4 DQ5 21 28 1 M28C16A 15 14 7 8
AI02113
A7 NC
A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2
AI02112
Warning: NC = Not Connected, DU = Don't Use. 2/19
Warning: NC = Not Connected, DU = Don't Use.
M28C16A, M28C17A
Table 2. Absolute Maximum Ratings (1)
Symbol TA T STG VCC V IO VI VESD Parameter Ambient Operating Temperature Storage Temperature Range Supply Voltage Input/Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model)
(2)
Value - 40 to 85 - 65 to 150 - 0.3 to 6.5 - 0.3 to VCC +0.6 - 0.3 to 6.5 3000
Unit C C V V V V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range.
Table 3. Operating Modes
Mode Read Write Standby / Write Inhibit Write Inhibit Write Inhibit Output Disable
Note: X = VIH or VIL
E VIL VIL VIH X X X
G VIL VIH X X VIL VIH
W VIH VIL X VIH X X
DQ0 - DQ7 Data Out Data In Hi-Z Data Out or Hi-Z Data Out or Hi-Z Hi-Z
DESCRIPTION (cont'd) The circuit has been designed to offer a flexible microcontroller interface featuring both hardware and software handshakingmode with Ready/Busy, Data Polling and Toggle Bit. The M28C16A/17A supports 32 byte page write operation. PIN DESCRITPION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/ Out (DQ0 - DQ7). Data is written to or read from the M28C16A/17A through the I/O pins.
Write Enable (W). The Write Enable input controls the writing of data to the M28C16A/17A. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. Ready/Busy is available for the M28C17A in PDIP, PLCC and SO packages, and for the M28C16A in TSOP only. OPERATION In order to prevent data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit resets all internal programming cicuitry. Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C16A/17Ais accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedancewhen either G or E is high.
3/19
M28C16A, M28C17A
Figure 3. Block Diagram
E G W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A10 (Page Address)
ADDRESS LATCH
64K ARRAY
A0-A5
ADDRESS LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING
AI01520
DQ0-DQ7
OPERATION (cont'd) Write Write operations are initiated when both W and E are low and G is high.The M28C16A/17Asupports both E and W controlled write cycles. The Address is latched by the falling edge of E or W which ever occurs last and the Data on the rising edge of E or W which ever occurs first. Once initiated the write operation is internally timed until completion. Page Write Page write allows up to 32 bytes to be consecutively latched into the memory prior to initiating a Figure 4. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
programming cycle. All bytes must be located in a single page address, that is A5 - A10 must be the same for all bytes. The page write can be initiated during any byte write operation. Following the first byte write instruction the host may send another address and data up to a maximum of tWHWH after the rising edge of E or W which ever occurs first. If a transition of E or W is not detected within tWHWH, the internal programming cycle will start. Microcontroller Control Interface The M28C16A/17A provides two write operation status bits and one status pin that can be used to minimize the system write cycle. These signals are available on the I/O port bits DQ7 or DQ6 of the memory during programming cycle only, or as the RB signal on a separate pin. Data Polling bit (DQ7). During the internal write cycle, any attempt to read the last byte written will produce on DQ7 the complementary value of the previously latched bit. Once the write cycle is finished the true logic value appears on DQ7 in the read cycle.
DP = Data Polling TB = Toggle Bit PLTS = Page Load Timer Status
4/19
M28C16A, M28C17A
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no longer driven.
20ns 0.4V to 2.4V 0.8V to 2.0V
Figure 5. AC Testing Input Output Waveforms
4.5V to 5.5V Operating Voltage 2.4V 2.0V 0.8V
Figure 6. AC Testing Equivalent Load Circuit
VCC
0.4V
IOL DEVICE UNDER TEST IOH OUT
2.7V to 3.6V Operating Voltage VCC - 0.3V 0.5 VCC 0V
AI02101B
CL = 30pF
CL includes JIG capacitance
AI02114
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 6. Read Mode DC Characteristics for M28C16A and M28C17A (TA = -40 to 85C, VCC = 4.5V to 5.5V)
Symbol ILI ILO ICC ICC1 ICC2
(1) (1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL and CMOS inputs) Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VIN VCC E = VIL, G = VIL , f = 5MHz E = VIH E > VCC - 0.3V
Min
Max 10 10 25 1 50
Unit A A mA mA A V V V V
VIL VIH VOL VOH
-0.3 2 IOL = 2.1 mA IOH = -400 A 2.4
0.8 VCC + 0.5 0.4
Note: 1. All I/O's open circuit.
5/19
M28C16A, M28C17A
Table 7. Power Up Timing for M28C16A and M28C17A (1) (TA = -40 to 85C, VCC = 4.5V to 5.5V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC VWI) Write Inhibit Threshold 1.5 Min Max 1 10 2.5 Unit s ms V
Note: 1. Sampled only, not 100% tested.
Table 8. Read Mode DC Characteristics for M28C16A-W (TA = -40 to 85C, VCC = 2.7V to 3.6V)
Symbol ILI ILO ICC ICC2
(1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current (TTL and CMOS inputs) Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VIN VCC E = VIL, G = VIL , f = 5 MHz E > VCC -0.3V
Min
Max 10 10 15 20
Unit A A mA A V V V V
VIL VIH VOL VOH
-0.3 2 IOL = 2.1 mA IOH = -400 A 0.8 VCC
0.6 VCC + 0.5 0.2 VCC
Note: 1. All I/O's open circuit.
Table 9. Power Up Timing for M28C16A-W (1) (TA = -40 to 85C, VCC = 2.7V to 3.6V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC VWI) Write Inhibit Threshold 1.5 Min Max 1 10 2.5 Unit s ms V
Note: 1. Sampled only, not 100% tested.
6/19
M28C16A, M28C17A
Table 10. Read Mode AC Characteristics for M28C16A and M28C17A (TA = -40 to 85C, VCC = 4.5V to 5.5V)
M28C16A / M28C17A Symbol Alt Parameter Test Condition min tAVQV tELQV tGLQV tEHQZ (1) tGHQZ (1) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -15 max 150 150 70 50 50 0 0 0 min -20 max 200 200 80 60 60 ns ns ns ns ns ns Unit
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 11. Read Mode AC Characteristics for M28C16-W (TA = -40 to 85C, VCC = 2.7V to 3.6V)
M28C16A / M28C17A Symbol Alt Parameter Test Condition min tAVQV tELQV tGLQV tEHQZ (1) tGHQZ (1) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -25 max 250 250 100 70 70 0 0 0 min -30 max 300 300 100 80 80 ns ns ns ns ns ns Unit
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
7/19
M28C16A, M28C17A
Figure 7. Read Mode AC Waveforms
A0-A10 tAVQV E tGLQV G tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA OUT Hi-Z
AI01511B
Note: Write Enable (W) = High
Toggle bit (DQ6). The M28C16A/17A offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 will toggle from "0" to "1" and "1" to "0" (the first read value is "0") on subsequentattempts to read any address in the memory. When the internalcycle is completedthe togglingwill stopand the device will be accessible for a new Read or Write operation.
Page Load Timer Status bit (DQ5). In the Page Write mode data may be latched by E or W up to tWHWH after the previous byte. Up to 32 bytes may be input. The Data output (DQ5) indicates the status of the internal Page Load Timer. DQ5 may be read by asserting Output Enable Low (tPLTS). DQ5 Low indicates the timer is running, High
8/19
M28C16A, M28C17A
Table 12. Write Mode AC Characteristics for M28C16A and M28C17A (TA = -40 to 85C, VCC = 4.5V to 5.5V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tWHRL tEHRL tDVWH tDVEH Alt tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDB tDB tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Write Enable High to Ready/Busy Low Chip Enable High to Ready/Busy Low Data Valid before Write Enable High Data Valid before Chip Enable High Note 1 Note 1 50 50 E = VIL, G = VIH G = VIH, W = VIL 100 0 0 0 0 0 0 200 100 0.2 30 5 100 100 Test Condition E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH Min 0 0 0 0 0 0 100 100 1 1 Max Unit ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns ns ns
Note: 1. With a 3.3 k external pull-up resistor.
9/19
M28C16A, M28C17A
Table 13. Write Mode AC Characteristics for M28C16-W (TA = -40 to 85C, VCC = 2.7V to 3.6V)
Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWHWH tWHRH tWHRL tEHRL tDVWH tDVEH Alt tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDB tDB tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Byte Load Repeat Cycle Time Write Cycle Time Write Enable High to Ready/Busy Low Chip Enable High to Ready/Busy Low Data Valid before Write Enable High Data Valid before Chip Enable High Note 1 Note 1 50 50 E = VIL, G = VIH G = VIH, W = VIL 200 0 0 0 0 0 0 200 200 0.4 50 5 250 250 Test Condition E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH Min 0 0 0 0 0 0 200 200 1 1 Max Unit ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns ns ns
Note: 1. With a 3.3 k external pull-up resistor.
10/19
M28C16A, M28C17A
Figure 8. Write Mode AC Waveforms - Write Enable Controlled
A0-A10 tAVWL E tELWL G tGHWL W
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWLDV DQ0-DQ7 DATA IN tDVWH RB
tWHWL
tWHDX
tWHRL
AI01512
Figure 9. Write Mode AC Waveforms - Chip Enable Controlled
A0-A10 tAVEL E tGHEL G tWLEL W
VALID tELAX
tELEH
tEHGL
tELDV DQ0-DQ7 DATA IN tDVEH RB tEHDX
tEHWH
tEHRL
AI01513
11/19
M28C16A, M28C17A
Figure 10. Page Write Mode AC Waveforms - Write Enable Controlled
A0-A10
Addr 0
Addr 1
Addr 2
Addr n
E tPLTS G tWHWL W tWLWH DQ0-DQ7 Byte 0 Byte 1 tWHWH Byte 2 tWHWH Byte n tWHRH
DQ5 tWHRL RB
Byte n
AI01514
Figure 11. Data Polling Waveform Sequence
A0-A10
Address of the last byte of the Page Write instruction
E
G
W
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI01516
12/19
M28C16A, M28C17A
Figure 12. Toggle Bit Waveform Sequence
A0-A10
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI01517
Note: 1. First Toggle bit is forced to '0'
13/19
M28C16A, M28C17A
ORDERING INFORMATION SCHEME Example: M28C16 - 20 W NS 6 T
Device Identifier C16 RB available only for the TSOP package C17 RB available T
Option Tape & Reel Packing
Speed 15 (1) 150 ns 20 25
(1) (2)
Operating Voltage blank 4.5V to 5.5V 5ms write W 2.7V to 3.6V 5ms write
Package BS PDIP28 MS SO28 300 mils NS TSOP28 8 x 13.4mm KA PLCC32
Temperature Range 6 -40 to 85 C
200 ns 250ns
30 (2) 300ns
Notes: 1. Available for M28C16A and M28C17A only. 2. Available for "W" Operating Voltage only.
Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a listof availableoptions (Speed, Package,etc... ) or for further informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
14/19
M28C16A, M28C17A
PDIP28 - 28 pin Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 14.99 33.02 15.24 1.52 mm Min - 0.38 3.56 0.38 - 0.20 36.83 - - 13.59 - - 15.24 3.18 1.78 0 28 Max 5.08 - 4.06 0.51 - 0.30 37.34 - - 13.84 - - 17.78 3.43 2.08 10 0.100 0.590 1.300 0.600 0.060 Typ inches Min - 0.015 0.140 0.015 - 0.008 1.450 - - 0.535 - - 0.600 0.125 0.070 0 28 Max 0.200 - 0.160 0.020 - 0.012 1.470 - - 0.545 - - 0.700 0.135 0.082 10
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Drawing is not to scale.
15/19
M28C16A, M28C17A
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb Typ A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Min 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ inches Min 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Drawing is not to scale.
16/19
M28C16A, M28C17A
SO28 - 28 lead Plastic Small Outline, 300 mils body width
Symb Typ A A1 A2 B C D E e H L N CP 1.27 mm Min 2.46 0.13 2.29 0.35 0.23 17.81 7.42 - 10.16 0.61 0 28 0.10 Max 2.64 0.29 2.39 0.48 0.32 18.06 7.59 - 10.41 1.02 8 0.050 Typ inches Min 0.097 0.005 0.090 0.014 0.009 0.701 0.292 - 0.400 0.024 0 28 0.004 Max 0.104 0.011 0.094 0.019 0.013 0.711 0.299 - 0.410 0.040 8
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Drawing is not to scale.
17/19
M28C16A, M28C17A
TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4mm
Symb Typ A A1 A2 B C D D1 E e L N CP 0.55 0.95 0.17 0.10 13.20 11.70 7.90 0.50 0 28 0.10 mm Min Max 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 0.70 5 0.022 0.037 0.007 0.004 0.520 0.461 0.311 0.020 0 28 0.004 Typ inches Min Max 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 0.028 5
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Drawing is not to scale.
A1
L
18/19
M28C16A, M28C17A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
19/19

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